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The Hard-Core Coder

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The Hard-Core Coder

Daily Archives: May 14, 2019

Full Adder Redux

14 Tuesday May 2019

Posted by Wyrd Smythe in CS101

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Tags

full adder, logic circuit, modeling, NOR gate, Python code, simulation, truth table

I’m returning to the full-adder logic circuit modeling to present the code for a version that tries to capture the timing of the signals.

The goal is to take a closer look at the intermediate states of the adder as signals trickle through it.

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Wyrd Smythe

Wyrd Smythe

The canonical fool on the hill watching the sunset and the rotation of the planet and thinking what he imagines are large thoughts.

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