14 Tuesday May 2019
Posted in CS101
I’m returning to the full-adder logic circuit modeling to present the code for a version that tries to capture the timing of the signals.
The goal is to take a closer look at the intermediate states of the adder as signals trickle through it.
08 Wednesday May 2019
This is the third post in the Full Adder series. The first post explored ways to code the abstract model of a full-adder. The second post explored one way to code a simulation of a physical system (where the models are of the components of the system).
This post explores another gate-based model, but one with only one type of gate. This simulation is close to being transistor-level.
07 Tuesday May 2019
In the last post, I explored different ways to model the logic of a full-adder. In this post I’ll explore a model of a physical instance of a full-adder — a model that simulates physical reality.
Because a full-adder is, at root, a mathematical expression, various software models can accomplish the same results. Models are abstractions, so the only thing a model can simulate perfectly is another model.
The Hard-Core Coder 